Conventional computer architectures include one or more computer processors which are connected to memory devices, and one or more peripheral devices for performing I/O operations. A typical computer architecture is shown with reference to FIG. 1. Data is transferred between computer processor 101 and I/O device 105. I/O device 105 can be any of a plurality of peripheral devices including disc drives, tape drives, printers, etc. I/O interface controller 103, shown interposed between computer processor 101 and I/O device 105 is responsible for controlling the transfer of information between computer processor 101 and I/O device 105.
Communications between computer processor 101 and I/O device 105 are conducted according to a predetermined format of signal transmission. This format allows the computer processor to selectively address and activate any of the devices coupled to the channel. The devices respond to predetermined address information, and interchange signals with the processor according to a predetermined format selected for the particular system.
A variety of predetermined formats (i.e. protocols) currently exist for enabling communication between computer processor 101 and I/O device 105. The I/O interface controller 103 addresses the concept of these varying formats of communication. These protocols include Message Level Interface (MLI), Small Computer System Interface (SCSI) and Intelligent Peripheral Interface (IPI).
These protocols differ, not only physically and electrically, but also in the quantity of data which may be handled and the manner in which handshaking is performed.
Several protocols transfer two bytes of data at one time, while other protocols may only transfer a single byte at a time. The MLI protocol transfers two bytes at once. The SCSI protocol transfers only a single byte at a time. The IPI protocol may transfer either a single or a double byte at once, depending upon the manner in which the I/O channel is programmed. Furthermore, when some channels receive two bytes of data, the position of the two bytes must be exchanged.
These protocols also differ in the manner in which control signals are exchanged between the computer processor and the I/O device to ensure that data is properly transferred between the two. Typically, when data is transmitted to the I/O interface controller, a strobe signal is simultaneously asserted. This strobe signal indicates to the I/0 interface controller that the data is valid and may be received. Strobe signals are handled in varying manners depending on the protocol being used. For example, a protocol may include an interlock mode in which a single strobe is fired to indicate that data is available for processing at this time. The processor then waits for a response before transmitting the next data word. If a protocol includes a throttle mode, multiple strobes are issued by the processor at a controlled rate. Thus, the transmission of every data word is accompanied by a strobe. The processor does not wait for an acknowledgement of a particular strobe before making the next data word available. If a protocol includes a mirror mode, the I/O device issues a plurality of strobes which are simply reflected back to the I/O device by the I/O interface controller. If a mirror mode is being used, however, the strobe rate is controlled by the I/O device.
Prior art I/O interface controllers have used various techniques to acknowledge receipt of a strobe. These techniques allow the incoming strobe to be acknowledged after first synchronizing the strobes to the internal clock signal of the I/O interface controller. This provides the necessary reliability factor which is desirable to prevent ill effects (such as data corruption). A high speed is generally achieved by using multi-phased clocks. If the chosen technology for implementation is such that it can tolerate very high frequency clock signals (e.g., 32 Mhz) (compared to the rate at which the interface between the I/O interface controller and either the host processor or the peripheral device operates), then the interfaces may be operated at near capacity throughput without undue complexity.
However, the slower technologies, for example CMOS (often chosen in data processing applications) cannot tolerate very high frequency clock signals. Their clock rate is very comparable to the rate at which the interface between the I/O interface controller and either the host processor or the peripheral device can operate. Thus, if the incoming strobe is synchronized before being acknowledged, then the synchronizing delay adds to the turnaround time of each strobe. This considerably reduces the overall performance of the I/O interface controller.
A variety of off-the-shelf chips are currently available for use as I/O interface controllers. These chips suffer from a variety of drawbacks. Each chip is designed to enable communications through only a single predetermined protocol. Furthermore, these chips require microprocessor type controllers to drive them. This requires additional hardware and logic. In addition, these chips cannot be used when the computer processor communicates using one protocol and the I/O device communicates using another incompatible protocol. Also, prior art I/O interface controllers, because they are monitoring the activity on two dissimilar interfaces (with the host processor and with the I/O device) typically require separate processors for monitoring each interface.